Bug fix for esp-idf 4.0, 4.1, 4.2 (code is different in 4.3): Add line: hal->half_duplex = dev->cfg.flags & SPI_DEVICE_HALFDUPLEX ? 1 : 0; To spi_setup_device() in components/driver/spi_master.c: static void SPI_MASTER_ISR_ATTR spi_setup_device(spi_host_t *host, int dev_id) { //if the configuration ...

I'm having the same problem, only on esp-idf 4+, works fine in 3.3.

Transactions are working fine, but as soon as I run a transaction with the half-duplex device, everything goes to hell on the other devices. See screenshots attached.

Hi - is anyone successfully using both of these modules with v4.x?

I'm testing with v4.1, although this problem is evident in v4.0 and v4.1-beta1. I tried master last night but couldn't compile. If I initialize wifi and then call esp_nimble_hci_and_controller_init() I get an abort. If I initialize NIMBLE and then call esp_wifi_start() I get an abort as well. I've p...

Thanks, I will test that out.

No, the bad bits can be low or high - and yes internal pull-up is on - if we don't use internal pull-up we get a lot of garbage on the input. Per my plot, it doesn't look to be an electrical issue, but rather a software or hardware bug in the processor. This is a chip-down design with the part # I r...

As mentioned, GPIO 10 is in the VSDIO power domain, which is 1.8V on this part.

Here is the initialization: QueueHandle_t uart_event_queue; const uart_config_t uart_config = { .baud_rate = 921600, .data_bits = UART_DATA_8_BITS, .parity = UART_PARITY_DISABLE, .stop_bits = UART_STOP_BITS_1, .flow_ctrl = UART_HW_FLOWCTRL_CTS_RTS, .rx_flow_ctrl_thresh = 120, }; uart_param_config(UA...

I can see from logic analyzer (both digital and analog) the data looks correct on the line, but the ESP32 is missing bits on occasion: The ESP32 saw: 6F 6E 6E 65 63 7 0 20 74 69 The correct bytes: 6F 6E 6E 65 63 7 4 20 74 69 uart error.PNG uart error2.PNG This is UART2 on pin 10 being routed via GPI...

Hello, any update?