Hardware: https://git.sweproj.com/ABC80/max80.git
Firmware: https://git.abc80.org/abc80/max80/fw.git

This is a bit offtopic here, I think, but feel free to PM me (or at least open up a separate thread) and I'd be happy to chat about a bunch of the options that got investigated and considered.

There is nothing "pseudo" about a delta-sigma DAC; it is one of the m most widely used DAC implementations out there.

The easy ways to do this are basically:

1. Resistor + schottky diode to 3.3 V Vcc
2. Voltage divider (two resistors)
3. 74HC/AC/AHC buffer (3 3 V Vcc)
4. 74CB3T/CBDT/CBT bus switch (in order of preference); these are bidirectional and almost zero latency!

Eh... ended up going with the platinum solution of using an FPGA for the bus interface; this was in no small part due to teaming up with a board designer willing to do the physical layout side of it, and because it really increased what could be done (HDMI output!) I'll post a couple of git links la...

Thank you for your information, this is really helpful. For Q8 you are referring to "Table 24-9", but tables in the document are numbered sequentially without chapter numbers and thus there is no table with that number. However, I presume you mean Figure 24-9. If I'm reading Figure 24-9 correctly, a...

Hi, I have somewhat successfully used the ESP32-S2 SPI unit as a JTAG master, but it has several issues that unfortunately require falling back to bitbanging several operations. JTAG is very closely related to SPI, but it has a couple of key differences which cause trouble. The signal mapping is bas...

OK, that is *not* what the ESP32-S2 technical manual states.

Hi, I would like to add the following feature additions to the ESP-IDF master SPI driver. They should be fairly trivial to implement, but there is no way to obtain this functionality at the moment without completely avoiding this driver. Specifically, I would like the post_cb function after a transa...

So if I'm reading it right, this is actually a documented erratum. Fractional bytes are lost on read; there doesn't seem to be anything anyone can do about it on existing hardware. I have worked around it by bitbanging any fractional byte at the end in read mode; it is slow but it works well enough ...

Too bad. A flow control feature would be wonderful; unfortunately the board I'm working on doesn't have enough signals wired up to do QSPI (I'm doing DIO, though.) What is really confusing to me is that HD appears to be an input in ESP32-x, but HOLD# is similarly an input on all flash chips I'm fami...