mikemoy wrote: ↑

Tue Apr 19, 2022 4:05 am

Did you check the docs?

Yes I have, but there is no relevant information. So presumably there is no configurable parameter for this but I nevertheless need to know the delay between /CS going low and the first SCK pulse.

I am interfacing the ESP32 as an SPI master to external logic at 80 MHz. I need to know, on the ESP32's SPI master operating at 80 MHz, how much time passes between /CS going low and the first SCK rising edge? Is this parameter configurable?

Thanks for any help you can provide.

Zane

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