Sorry, we cannot use that thirdparty C6 + P4 SoM. The onboard C6’s USB is not exposed which may impede the development of it, and only 5 of 16 LP GPIOs of P4 are led out to the castellated holes. It’s not suitable for those who want to run some IO-intensive workloads on the LP subsystem, such as usi...

Hi Espressif: ESP32-P4 had been announced days ago, but there’re no news about any module of P4. Is there any proposal to release any standalone SoM of P4, and pre-certified combo SoMs paired with an RF SoC, just like ESP32-DU1906-U? Some basic devkits of these modules with only MIPI, USB and GPIO h...

Recently some chip’s (c3 and h2, but see soc/boot_mode.h, may be others) updated TRM added yet another boot mode other than original SPI boot and joint download mode, the SPI download mode. How can I leverage this newly documented functionality?

Seems like an upcoming dual-core BLE SoC. Not publicly announced yet.

https://www.espressif.com/zh-hans/news/CES2024

Hello folks: After reading the datasheet and documentation, I found that esp32-s3 can address up to 16MiB of PSRAM with memory-mapped reading/writing under the current mapping scheme supported by ESP-IDF. But all available modules/kits on the market have 8MiB of PSRAM at most only. Is there any plan...

Hello, I found some discrepancies in the datasheets of esp32-s3, esp32-s3-wroom-1(U) and esp32-s3-wroom-2, default function of GPIO 19/20 (in bold): https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf In the ESP32-S3 (mcu), p14, saying USB_D+/- https://www.espressif...

Thanks. Do they have any breaking change we should pay extra attention to if we tried to develop with newer ESP32-S3-DevKitC-1-N32R8V but integrating ESP32S3-WROOM-1U-N16R8 into our final products?

What are the differences between WROOM-2-N16R8V and WROOM-1U-N16R8, excluding voltage level of VDD_SPI and on-board antenna.

Dear,

I have an ESP32-S3-DEVKITC-2, which embeds an ESP32-S3R8V and factory burnt EFUSE_VDD_SPI_FORCE. According to the datasheet, VDD_SPI is forced to 1v8 regardless of the status of strapping pin GPIO45. Should I use GPIO45 as a normal GPIO pin?