Hi,

which esp-idf version are you using? I had the same issue: https://github.com/espressif/esp-idf/issues/5425
As far, as I know, the fix is yet not released in all available versions.

Alex

ha0x2328 wrote: ↑

Mon Jul 13, 2020 8:38 pm

Thank you, do you have an working example schematic without external oscillator?

https://github.com/alexreinert/PCB/blob ... RF-ETH.pdf

GPIO5 is propably not the best solution as it is driven high on bootup, which will enable the oscillator which possible pulls the GPIO0 low and enters the download mode. So use a GPIO, which is not a strapping pin or do not use an oscillator at all and use the clock out mode on GPIO17 as clock for t...

This is strange. I would understand if it was the Software Reset bit that was written but in this case it's the Power Down bit which should not trigger a reset (and thus require some delay). The delays mentioned in the datasheet are all in the sub-millisecond range other than the power supply to RS...

It is interesting that the EVB uses GPIO0 for all the problems this can cause. I use GPIO0 so I cannot tell you! As I understood, Olimex did the design at a time where were no support for the clock output on GPIO17 in esp-idf. On the ESP32-PoE-ISO they changed the design and use the GPIO17 instead ...

@deimos: thanks for sharing your issue. I did not find any mention in the datasheet of a register update delay/timing though. Do you think it could be related to a clocking issue (i.e a late startup of the clock or clock stability error) ? It is not an issue on updating register in generel, it is j...

Hi,

have a look at https://github.com/espressif/esp-idf/issues/5425
Maybe this solves your problem.

Alex

Hi,

I designed a board using the LAN8720A using the clockout of the ESP on GPIO17.
The hardware works perfectly, but I had a software issue on IDF 4.0.1 (see https://github.com/espressif/esp-idf/issues/5425).

Alex