I have a few questions. I see some elements of cfg.gpio_bus are set to -1 and commented with designations for UART1 RX/TX, SPI flash, etc. Am I correct in assuming those are device specific pins that simply happen to align with the default code assigning inputs to the corresponding array indexes? .....

I can confirm strapping GPIO 15 to ground + setting "Core Debug Level" to none works.

Thank You E.U.A. This looks excellent!

Mmmm...so much data ...