Updates: 1. I could not get the CDC console example working on esp32s3, due to compilation error: C:/Users/null/esp/esp-idf/components/esp_system/port/soc/esp32s3/usb_console.c:69:1: error: static assertion failed: "usb_osglue_*_int is not multicore capable" The flag CONFIG_ESP_CONSOLE_USB_CDC is se...

Thank you for the suggestion. Running addr2line on the bootloader .elf file also does not return any functions; inspected the map file - these addresses are not in there.

Hi, tried the code without the chip_usb_set_persist_flags(USBDC_BOOT_DFU) statement, the result is the same.

I am attemting to restart an ESP32S3 into DFU mode, but each time I issue esp_restart(), I get an error: /*---------------------------------------------------------------------------*/ /* CODE */ static void reboot_to_dfu(void) { ESP_ERROR_CHECK(esp_register_shutdown_handler(usb_persist_shutdown_han...

Saving a large (<1K) blob into NVS results in a reset due to watchdog trigger. The problem does not appear every time the operation is performed. Details of the application: - Support for power management is enabled - RTC watchdog period 9000 ms - Task watchdog timer set for 5 sec - NVS size: 16 KB ...

@ESP_Sprite,thank you for the input - I burned fuse DIS_USB_JTAG and now I can connect to ESP32S3 using ESP-Prog. Flashing over JTAG works. I still have one issue. I am starting openocd from a terminal using `openocd -c 'set ESP_RTOS none' -f board/esp32s3-ftdi.cfg`, and then starting GDB from VS Co...

The fuse USB_PHY_SEL has been set to True, so trying to connect to USB-JTAG results in: ./bin/openocd -f board/esp32s3-builtin.cfg Open On-Chip Debugger v0.11.0-esp32-20221026 (2022-10-26-14:47) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Info : only one ...

openocd complains, but the connections appear fine. GPIO3 is pulled to 3.3V. I can't connect via USB to JTAG either. Where should I look for the cause? I am also attaching fuse dump. junk@yard:~/.espressif/tools/openocd-esp32/v0.11.0-esp32-20221026/openocd-esp32$ ./bin/openocd -f share/openocd/scrip...

@ESP_Sprite - I overlooked your previous answer somehow - the function you referred to works: ESP-ROM:esp32s3-20210327 Build:Mar 27 2021 rst:0x3 (RTC_SW_SYS_RST),boot:0x20 (DOWNLOAD(USB/UART0)) Saved PC:0x403758f1 waiting for download The chip I am testing the function on is manufactured before June...

Turns out if you issue a software reset and keep GPIO0 low, the device does not enter DFU mode. So what's left is to have a GPIO trigger an external circuit which asserts both reset and boot signals.